With high integration density, high performance and high-speed operation of semiconductor chips, much effort has been attempted to downsize and mass-produce semiconductor packages. For example, the semiconductor package has been proposed, which directly and electrically connects pads of a semiconductor chip and electrode terminals of a printed circuit board through bumps, which are made of solder or metal and formed on the pads of the semiconductor chip.
A typical semiconductor package using the bump which is made of solder may be a flip chip ball grid array (FCBGA) package or a wafer level chip scale package (WLCSP). Meanwhile, a package using the bump which is made of metal may be a chip-on-glass (COG) package or a tape carrier package (TCP).
The FCBGA package may be fabricated by electrically connecting solder bumps coming in contact with pads of a semiconductor chip to pads of a substrate, performing underfill to protect the solder bumps from external environment or mechanical problems, attaching solder balls on the rear of the substrate which comes in contact with the semiconductor chip, and electrically connecting the solder bumps with the electrode terminals of a printed circuit board. Meanwhile, the method of fabricating the WLCSP redistributes or reconfigures electrode pads to provide light, thin, short and small products, and equalizes the sizes of a chip and a package through metal bumps.
The chip-on-glass method manufactures the semiconductor package by forming metal bumps on pads of a semiconductor chip, and electrically connecting the pads of the semiconductor chip to electrode terminals of a printed circuit board by thermal compression and hardening through medium composed of polymer containing anisotropic conductive particles.
FIGS. 1 through 4 partially illustrate a redistribution process and a bumping process in the WLCSP method.
As illustrated in FIG. 1, an electrode pad 15 is formed on a substrate 10, and an insulating layer 20 exposes the top surface of the electrode pad 15. To redistribute the electrode pad, a polymer layer 30 with an opening is formed on the top surface of the electrode pad. An area of the electrode pad 15 extended for the redistribution is illustrated in a plan view of FIG. 2.
As illustrated in FIG. 3, a metal bump structure for a semiconductor package comprises a passivation layer 20 selectively exposing a chip pad above a semiconductor chip 10, a polymer layer 30 reconfiguring the chip pad, a metal interconnection 40 forming the pad and redistributed on the polymer layer 30, a polymer layer 50 protecting the redistributed metal interconnection, UBMs 60 and 70 formed on the redistributed pad, and a metal bump 80 formed on the UBMs 60 and 70. FIG. 4 illustrates the electrode pad portion of FIG. 1 and the bump portion of FIG. 3 on the whole.
As semiconductor chips are being made with high integration density and high performance, a driving current increases. As operating speed of the semiconductor chip increases, its operation frequency increases as well. However, the tendency creates many problems in the redistribution/metal bump structure of a conventional wafer level chip size/scale package. For example, an interface crack occurs due to the atomic migration and electromigration at the interface between the UBM and the metal bump at high current/high frequency. Furthermore, as the chips are downsized, and the operation frequency gets higher, signal delay and distortion are worse.
Therefore, the present invention has been made in view of the above-mentioned problems, and it is an objective of the present invention to improve electrical properties of a wafer level chip scale package (WLCSP) operating at high frequency and high current.
It is another objective of the present invention to reduce an interface crack caused by atomic migration and electromigration at the interface between an UBM (under bump metallurgy) and a metal bump.
It is yet another objective of the present invention to provide a bump for a semiconductor package capable of increasing a contact area between an electrode pad and a metal bump, thereby to improve contact reliability.
It is yet still another objective of the present invention to increase resistance against thermal stress of a mounted semiconductor package, thereby to improve mechanical reliability.
According to an exemplary embodiment of the present invention, there is provided a bump for a semiconductor package, which comprises an electrode pad formed above a semiconductor chip, a polymer layer formed on the electrode pad and having a plurality of vias, an UBM formed on the polymer layer having the plurality of vias, and a metal bump bonded on the UBM
According to another exemplary embodiment of the present invention, there is provided a bump for a semiconductor package, which comprises an electrode pad redistributed above a semiconductor chip, a polymer layer formed on the electrode pad and having a plurality of vias, an UBM formed on the polymer layer having the plurality of vias, and a metal bump bonded on the UBM. The redistributed electrode pad may be one redistributed from the electrode pad of a first region. In this case, a polymer layer having a plurality of vias may be formed on the electrode pad located at the first region.
According to another exemplary embodiment of the present invention, there is provided a bump for a semiconductor package, which comprises an electrode pad and/or a redistribution electrode pad formed above a semiconductor chip, a polymer layer formed on the electrode pad and/or the redistribution electrode pad and having a plurality of vias, a stress relaxation layer formed above the polymer layer having the plurality of vias, an UBM formed on the polymer layer having the plurality of vias, and a metal bump bonded on the UBM.
The metal bump may be composed of at least one selected from the group consisting of gold, gold alloy, copper, copper alloy, nickel, nickel alloy, aluminum, aluminum alloy, silver, silver alloy, eutectic solder (Sn/37Pb), high lead solder (Sn/95Pb), and lead-free solder having Sn of 30% or more (SnAg, SnCu, SnZn, SnZnBi, SnAgCu, SnAgBi, SnAgCuNi, and the like).
The electrode pad of the semiconductor chip may be composed of at least one selected from the group consisting of titanium, titanium alloy, aluminum, aluminum alloy, nickel, nickel alloy, copper, copper alloy, chromium, chromium alloy, gold, gold alloy, silver, silver alloy, and lead-free solder containing tin (Sn).
The UBM may have a structure of three layers including an adhesion layer having excellent adhesive strength with the electrode pad or the redistribution electrode pad, a diffusion-barrier layer preventing diffusion from the metal bump to the electrode pad, and a wetting layer having excellent wettability with the metal bump. Alternatively, the UBM may have a structure of two layers (the adhesion layer and the diffusion-barrier layer, the adhesion layer and the wetting layer, the diffusion-barrier layer and the wetting layer).
The adhesion layer may be composed of at least one selected from the group consisting of titanium, titanium alloy, chromium, chromium alloy, copper, copper alloy, nickel, nickel alloy, gold, gold alloy, aluminum, aluminum alloy, vanadium, and vanadium alloy.
The diffusion-barrier layer may be composed of at least one selected from the group consisting of nickel, nickel alloy, copper, copper alloy, vanadium, and vanadium alloy, aluminum, aluminum alloy, gold, gold alloy, cobalt, cobalt alloy, manganese, and manganese alloy.
The wetting layer may be composed of at least one selected from the group consisting of copper, copper alloy, nickel, nickel alloy, gold, gold alloy, aluminum, aluminum alloy, cobalt, cobalt alloy, manganese, manganese alloy, and lead-free solder containing tin (Sn) of 30% or more.
The adhesion layer may have a thickness of about 0.01 μm to about 1 μm, and the diffusion-barrier layer may have a thickness of about 1 μm to about 10 μm, and the wetting layer may have a thickness of about 1 μm to about 10 μm, and the UBM may have a thickness of about 0.1 μm to about 100 μm.
The metal bump may be formed inside and outside the vias of the polymer layer.
The polymer layer may be photosensitive and composed of at least one selected from an organic substance including polyimide, benzocyclobutene (BCB), epoxy resin, and siloxane or silicone resin, an inorganic substance including SiO2 and SiN, and a mixture of the organic and inorganic substances.
The polymer layer having the plurality of vias may comprise an insulating material having a dielectric constant of 1.0 or more. The via of the polymer layer may have a circular shape, or any one selected from a polygonal shape such as a quadrangular shape, a pentagonal shape, a hexagonal shape, and an octagonal shape. The polymer layer having the plurality of vias may have a thickness of about 0.1 μm to about 100 μm, and a ratio of thickness to opening width of about 0.5 or more.
A total area of the plurality of vias of the polymer layer may be 10% or more compared to that of the electrode pad, and a total surface area of the vias may be 50% or more compared to that of the electrode pad.
In accordance with another aspect of the present invention, there is provided a method of fabricating a bump for a semiconductor package. The method comprises the steps of forming a polymer layer having a plurality of vias on an electrode pad above a semiconductor chip, forming an UBM on the polymer layer, and forming a metal bump on the UBM.
The method may further comprise the step of forming a stress relaxation layer formed above the polymer layer having the plurality of vias. Further, the method may further comprise the step of redistributing the electrode pad.
The polymer layer having the plurality of vias may be formed using any one selected from coating, immersion, dry film deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), and evaporation.
The UBM may be formed using any one selected from PVD, CVD, evaporation, electroplating, electroless plating, and screen printing.
The metal bump may be formed using any one selected from electroplating, electroless plating, evaporation, ball attach, ball placement, screen printing, and solder jet.
The present invention also provides a semiconductor package including the bump.
According to the present invention, a polymer layer having a number vias is formed on an electrode pad or a redistribution electrode pad formed above a semiconductor chip, thereby increasing an electrical surface area and a physical contact area between the electrode pad and a metal bump. Since current crowding is prevented and current dispersion occurs by the plurality of vias, current density between the electrode pad and the metal bump decreases. Accordingly, occurrence of the interface crack caused by a joule heating effect and atomic migration/electromigration which occur at the metal bump having a fine pitch is suppressed, thereby to increase a lifetime of the package. Further, a contact area between the electrode pad and the metal bump increases, thereby to improve joint reliability.
In addition, since the polymer layer for relieving stress is formed below the metal bump, although stress generated by a thermal expansion coefficient difference between a substrate and a semiconductor chip after device mounting is concentrated to the metal bump, the polymer layer serves to relieve the stress, thereby to improve mechanical reliability of the package.